SH7764 Datasheet, PDF (1288/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.5.7 Data Enable Signal (Composite)
Either the data enable signal generated in the graphics blocks (obtained by logically ORing signals
for layers 1 to 4) or the date enable signal (rectangle) generated in the display control block can be
selected through the DEC_MODE bit in SGMODE.
Internal HSYNC
Internal HSYNC
The data enable signal is asserted
for the graphic image display areas
of layers 1 to 4.
Layers 1 to 4
The data enable signal generated
in the display control area is asserted
for this area.
Figure 24.6 Data Enable Signals
Rev. 1.00 Nov. 22, 2007 Page 1232 of 1692
REJ09B0360-0100