SH7764 Datasheet, PDF (350/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
14 to 12 IWRRS2 to 111
R/W
IWRRS0
11, 10 
All 0
R
9, 8
SZ1 and Undefined R
SZ0
Description
Idle Cycles between Read and Read Access Cycles to
Same Area (Area 0)
These bits specify the number of idle cycles to be
inserted after a read access to the memory connected
to area 0.
The idle cycles specified in these bits are inserted
between consecutive read and read access cycles to
the same area (area 0).
000: No idle cycles inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Width
The external pins (MODE4 and MODE3) for specifying
the bus width are sampled at a power-on reset.
00: Reserved
01: 8 bits
10: 16 bits
11: 32 bits
Rev. 1.00 Nov. 22, 2007 Page 294 of 1692
REJ09B0360-0100