SH7764 Datasheet, PDF (1027/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Table 21.19 Buffer Status Indicated by the BSTS Bit
ISEL or DIR
BSTS
0 (receiving direction) 0
0 (receiving direction) 1
1 (transmitting
0
direction)
1 (transmitting
1
direction)
Buffer Memory State
There is no received data, or data is being received.
Reading from the FIFO port is inhibited.
There is received data, or a zero-length packet has been
received.
Reading from the FIFO port is allowed.
However, because reading is not possible when a zero-
length packet is received, the buffer must be cleared.
The transmission has not been finished.
Writing to the FIFO port is inhibited.
The transmission has been finished.
CPU write is allowed.
Table 21.20 Buffer Status Indicated by the INBUFM Bit
IDIR
0 (receiving direction)
1 (transmitting
direction)
INBUFM
Invalid
0
1 (transmitting
1
direction)
Buffer Memory State
Invalid
The transmission has been finished.
There is no waiting data to be transmitted.
The FIFO port has written data to the buffer.
There is data to be transmitted
Rev. 1.00 Nov. 22, 2007 Page 971 of 1692
REJ09B0360-0100