SH7764 Datasheet, PDF (814/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.6 E-MAC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the E-MAC. The information in this register is reported in the form
of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only
bit that is not cleared by writing 1) and are not affected by writing 0. Each interrupt source can
also be masked by means of the corresponding bit in the E-MAC/E-DMAC status interrupt
permission register (EESIPR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— TWB —
—
— TABT RABT RFCOF ADE ECI TC TDE TFUF FR RDE RFOF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
—
—
—
— CND DLC CD TRO RMAF —
Initial value: 0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R
5
4
3
2
1
0
— RRF RTLF RTSF PRE CERF
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
31

30
TWB
29 to 27 
Initial
Value
0
0
All 0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write-Back Complete
Indicates that write-back from the E-DMAC to the
corresponding descriptor after frame transmission has
completed. This operation is enabled only when the TIS
bit in TRIMD is set to 1.
0: Write-back has not completed, or no transmission
directive
1: Write-back has completed
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 758 of 1692
REJ09B0360-0100