SH7764 Datasheet, PDF (1594/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 List of Registers
Module
Register Name
P4 Area
Abbreviation R/W Address*
Area 7
Address*
Access
Size Remarks
UBC
Match data mask setting CDMR1
register 1
R/W H'FF20 0034 H'1F20 0034 32
Execution count break CETR1
register 1
R/W H'FF20 0038 H'1F20 0038 32
Channel match flag
register
CCMFR
R/W H'FF20 0600 H'1F20 0600 32
Break control register CBCR
R/W H'FF20 0620 H'1F20 0620 32
Notes: * The P4 area addresses shown here are the P4 area addresses in the virtual address
space. The area 7 addresses should be accessed via the area 7 in the physical address
space using the TLB.
1. Only 0 can be written to the HE and TE bits in CHCR after 1 is read from the bits to
clear the flags.
2. Only 0 can be written to the AE and NMIF bits in DMAOR after 1 is read from the bits to
clear the flags.
3. Do not access the registers with the access size not specified here.
4. Only 0 can be written to the registers to clear the flags. In addition, bits 15 to 8, 3, and
2 are read-only bits allowing no write-accesses.
5. Only 0 can be written to the registers to clear the flags. In addition, bits 15 to 1 are
read-only bits allowing no write-accesses.
6. Only 0 can be written to bits 4 to 0 to clear the flags.
7. Only 0 can be written to bits 6 to 0 to clear the flags.
8. All the bits except bits 27 and 26 in the registers are read-only bits; bits 27 and 26 allow
both read- and write- accesses. For details, refer to section 18.3.17, Status Registers 0
to 5 (SSISR0 to SSISR5).
9. Bits 15 to 3 are read-only bits. Only 0 can be written to bits 2 to 0 after 1 is read from
the bits.
10. The registers can only be accessed in 16-bit units; be sure to access the registers with
the specified access size.
11. For the standby control register, also refer to figure 9.1, Block Diagram of CPG.
Rev. 1.00 Nov. 22, 2007 Page 1538 of 1692
REJ09B0360-0100