SH7764 Datasheet, PDF (535/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Timer Unit (TMU)
Initial
Bit
Bit Name Value R/W Description
7, 6
ICPE[1:0]*¹ 00
R/W Input Capture Control
These bits, provided in channel 2 only, specify whether
the input capture function is used, and control enabling
or disabling of interrupt generation when the function is
used.
The CKEG bits specify whether the rising edge or falling
edge of the TCLK pin is used to set the TCNT2 value in
TCPR2.
The TCNT2 value is set in TCPR2 only when the ICPF
bit in TCR2 is 0. When the ICPF bit is 1, TCPR2 is not
set in the event of input capture.
00: Input capture function is not used.
01: Setting prohibited
10: Input capture function is used, but interrupt due to
input capture (TICPI2) is not enabled.
Data transfer request is sent to the DMAC in the
event of input capture.
11: Input capture function is used, and interrupt due to
input capture (TICPI2) is enabled.
5
UNIE
0
R/W Underflow Interrupt Control
Controls enabling or disabling of interrupt generation
when the UNF status flag is set to 1, indicating TCNT
underflow.
0: Interrupt due to underflow (TUNI) is disabled
1: Interrupt due to underflow (TUNI) is enabled
4, 3
CKEG[1:0] 00
R/W Clock Edge
These bits select the external clock input edge when an
external clock is selected or the input capture function is
used.
00: Count/input capture register set on rising edge
01: Count/input capture register set on falling edge
1X: Count/input capture register set on both rising and
falling edges
Rev. 1.00 Nov. 22, 2007 Page 479 of 1692
REJ09B0360-0100