SH7764 Datasheet, PDF (1376/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
26.2.1 SRC Input Data Register (SRCID)
SRCID is a 32-bit readable/writable register that is used to input the data before sampling rate
conversion. All the bits are read as 0. The data input to SRCID is stored in the 16-stage input data
FIFO. When the number of data in input data FIFO is 16, writing to SRCID is invalid. For stereo
data, bits 31 to 16 are for ch 0 data, and bits 15 to 0 are for ch 1 data. For monaural data, data in
bits 31 to 16 is valid, and data in bits 15 to 0 is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The data subject to sampling rate conversion is aligned differently depending on the IED bit
setting in SRCIDCTRL. Table 26.3 shows the relationship between the IED bit setting and data
alignment.
Table 26.3 Alignment of Data before Sampling Rate Conversion
IED
ch0[15:8]
ch0[7:0]
ch1[15:8]
ch1[7:0]
0
SRCID[31:24]
SRCID[23:16]
SRCID[15:8]
SRCID[7:0]
1
SRCID[23:16]
SRCID[31:24]
SRCID[7:0]
SRCID[15:8]
Rev. 1.00 Nov. 22, 2007 Page 1320 of 1692
REJ09B0360-0100