SH7764 Datasheet, PDF (507/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
INT2B5: Indicates detailed interrupt sources for the FLCTL.
Module
FLCTL
Bit
31 to 4
3
2
1
0
Source Function
Description
—
These bits are always read as 0. The
write value should always be 0.
FLTRQ1 FLCTL FLECFIFO transfer request
interrupt
FLTRQ0 FLCTL TLDFIFO transfer request
interrupt
FLTEND FLCTL transfer end interrupt
Indicates FLCTL
interrupt sources. This
register indicates
FLCTL interrupt
sources even if mask
setting is made in the
interrupt mask register
for them.
FLSTE FLCTL status error or ready/busy
timeout error interrupt
INT2B6: Indicates detailed interrupt sources for the SCIF2.
Module
SCIF2
Bit
31 to 4
3
2
Source Function
Description
—
TXI2
BRI2
These bits are always read as 0. The
write value should always be 0.
SCIF channel 2 transmit FIFO data
empty interrupt
SCIF channel 2 break interrupt or
overrun error interrupt
Indicates SCIF2
interrupt sources. This
register indicates the
SCIF2 interrupt sources
even if mask setting is
made in the interrupt
mask register for them.
1
RXI2 SCIF channel 2 receive FIFO data full
interrupt or receive data ready
interrupt
0
ERI2 SCIF channel 2 receive error interrupt
Rev. 1.00 Nov. 22, 2007 Page 451 of 1692
REJ09B0360-0100