SH7764 Datasheet, PDF (882/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
21.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG)
D0FBCFG is a register that controls DMA0-FIFO bus accesses. D1FBCFG is a register that
controls DMA1-FIFO bus accesses.
These registers are initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
DFACC
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15, 14 
13, 12 DFACC
11 to 0 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
00
R/W DMAn-FIFO Buffer Access Mode (n = 0, 1)
Specifies DMA0-FIFO or DMA1-FIFO port access
mode.
00: Cycle steal mode (initial value)
01: 16-byte continuous access mode
10: 32-byte continuous access mode
11: Invalid
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 826 of 1692
REJ09B0360-0100