SH7764 Datasheet, PDF (1340/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.3.1 Common Control Register (FLCMNCR)
FLCMNCR is a 32-bit readable/writable register that specifies the type (NAND) of flash memory,
access mode, and FCE pin output.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
SNAND
QT
SEL
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FCK
SEL
— ECCPOS[1:0]
ACM[1:0]
NAND
WF
—
—
—
—
— CE0 —
—
TYPE
SEL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R/W R/W R/W R R R R R R/W R R R/W
Initial
Bit
Bit Name Value R/W Description
31 to 19 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18
SNAND 0
R/W Large-Capacity NAND Flash Memory Select
This bit is used to specify 1-Gbit or larger NAND flash
memory with the page configuration of 2048 + 64 bytes.
0: When flash memory with the page configuration of
512 + 16 bytes is used.
1: When NAND flash memory with the page
configuration of 2048 + 64 bytes is used.
Note: When TYPESEL = 0, this bit should not be
set to 1.
Rev. 1.00 Nov. 22, 2007 Page 1284 of 1692
REJ09B0360-0100