SH7764 Datasheet, PDF (784/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.20 Automatic PAUSE Frame Register (APR)
APR is used to set the TIME parameter value of an automatic PAUSE frame. When an automatic
PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the
PAUSE frame.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
AP[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 16 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 AP[15:0] All 0 R/W Automatic PAUSE
These bits set the TIME parameter value of an
automatic PAUSE frame. One bit is equivalent to 512
bit-time.
Rev. 1.00 Nov. 22, 2007 Page 728 of 1692
REJ09B0360-0100