SH7764 Datasheet, PDF (264/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches
The SH-4A has an IC way prediction scheme to reduce power consumption. In addition, memory-
mapped associative writing, which is detectable as an exception, can be enabled by using the non-
support detection exception register (EXPMASK). For details, see section 5, Exception Handling.
Virtual address
31
12 10
54 2 0
Entry selection
[12:5]
Longword (LW) selection
22
Address array
8
(way 0 to way 3)
3
Data array
(way 0 to way3)
LRU
0
Tag
UV
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
255 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits ^{6 bits}
Comparison
(Way 0 to way 3)
Read data
Write data
Hit signal
Figure 8.1 Configuration of Operand Cache (Cache size = 32 Kbytes)
Rev. 1.00 Nov. 22, 2007 Page 208 of 1692
REJ09B0360-0100