SH7764 Datasheet, PDF (337/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
Description
63 to 32 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
31
LTE
0
R/W
Linear-to-Tiled Memory Address Translation Enable
This bit enables linear-to-tiled memory address
translation to be performed in the space specified by
the LTAD and LTAM registers.
30 to 13 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
12 to 9 LTMWX3 H'0
R/W
Memory Width Setting
to
LTMWX0
These bits specify the image area width.
0001: 512
0010: 1024
0100: 2048
1000: 4096
Other than above: Setting prohibited.
8 to 1 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
LTGBM 0
R/W
16 Bits Per Pixel Graphics Mode Enable
This bit specifies the graphics mode.
0: 8 bits per pixel
1: 16 bits per pixel
Note: This register should be set while the SDRAM is not accessed by any modules; for example,
during initial setting after a power on (except for auto-refreshing).
Rev. 1.00 Nov. 22, 2007 Page 281 of 1692
REJ09B0360-0100