SH7764 Datasheet, PDF (314/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.2 Input/Output Pins
Table 11.1 shows the MCU pin configuration.
Table 11.1 MCU Pin Configuration
Pin Name
A25 to A0
D63 to 32
Function
Address bus
Data bus
D31 to D0
BS
CS3 to CS0
Data bus
Bus cycle start
Chip select
RD
Read
R/W
Read/write
RAS
CAS
CKE
DQMLL
DQMLU
DQMUL
DQMUU
WE0
Row address strobe
Column address strobe
Clock enable
Data mask
Data mask
Data mask
Data mask
Data enable 0
I/O
Description
Output Address output
I/O
Data input/output (multiplexed with the other
pins)
I/O
Data input/output
Output Signal that indicates the start of a bus cycle.
Output Chip select signal that indicates the area being
accessed.
Output Read signal from the external device
Output Data bus input/output direction designation
signal. Also used as WE signal during SDRAM
access.
Output SDRAM RAS signal
Output SDRAM CAS signal
Output SDRAM clock enable signal
Output SDRAM data mask signal for D7 to D0
Output SDRAM data mask signal for D15 to D8
Output SDRAM data mask signal for D23 to D16
Output SDRAM data mask signal for D31 to D24
Output During SRAM access: write strobe signal for
D7 to D0.
When setting SDRAM interface: data mask
signal for D39 to D32 (high active)
Rev. 1.00 Nov. 22, 2007 Page 258 of 1692
REJ09B0360-0100