SH7764 Datasheet, PDF (1351/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Bit
11 to 0
Initial
Bit Name Value
DTCNT[11:0] H'000
R/W Description
R/W Data Count Specification
Specify the number of bytes of data to be read or written
in command access mode. (Up to 2048 + 64 bytes can be
specified.)
25.3.7 Data Register (FLDATAR)
FLDATAR is a 32-bit readable/writable register. It stores input/output data used when 0 is written
to the CDSRC bit in FLCMDCR in command access mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DT[31:24]
DT[23:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DT[15:8]
DT[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 24 DT[31:24] H'00
R/W Fourth Data
Specify the 4th data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
23 to 16 DT[23:16] H'00
R/W Third Data
Specify the 3rd data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
Rev. 1.00 Nov. 22, 2007 Page 1295 of 1692
REJ09B0360-0100