SH7764 Datasheet, PDF (563/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
TEND
1
R/(W)* Transmit End
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
• TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR
1: End of transmission
[Setting conditions]
• TEND is set to 1 when the chip is a power-on
reset
• TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
• TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
Rev. 1.00 Nov. 22, 2007 Page 507 of 1692
REJ09B0360-0100