SH7764 Datasheet, PDF (835/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.17 Transmit Buffer Read Address Register (TBRAR)
TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the
transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC
can be recognized by monitoring addresses displayed in this register. The address from which the
E-DMAC is actually reading in the buffer may be different from the value read from this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBRA[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TBRA[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 0 TBRA[31:0] All 0
R
Transmission-Buffer Read Address
These bits can only be read. Writing is prohibited.
Rev. 1.00 Nov. 22, 2007 Page 779 of 1692
REJ09B0360-0100