SH7764 Datasheet, PDF (387/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.7.6 Single Write
Figure 11.15 shows the single write timing chart, in which it is assumed that data is 64 bits wide,
bank close mode is used, and the burst length is four. Even during single write, data is written
assuming that the burst length is four, like during burst write; however, during the unnecessary
data cycles, DQMn is asserted to mask the unnecessary data write.
If there are unused cycles, the memory access time increases, reducing program execution speed
and DMA transfer speed. To prevent this, it is important to use such a data structure that allows
placing data on 32-byte boundaries thus enabling data transfer in units of 32 bytes.
CLKOUT
CKE
Bank
address
Precharge
-sel
Address
CSn
R/W
RAS
CAS
DQMn
D[63:0]
(write)
BS
DACKn
(Active-low)
D0 D1 D2 D3
⋅ Transfer size: 32 bytes
⋅ External bus: 64 bits wide
⋅ BL: 4 bursts
⋅ CL: 3
Figure 11.15 Basic SDRAM Interface Timing (4) Single Write
Rev. 1.00 Nov. 22, 2007 Page 331 of 1692
REJ09B0360-0100