SH7764 Datasheet, PDF (1698/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
33.4.13 H-UDI Module Signal Timing
Table 33.31 H-UDI Module Signal Timing
Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35,
Ta = –20 to 85°C, –40 to 85°C
Module
Item
Symbol Min.
H-UDI
Input clock cycle
t
50
TCKcyc
Input clock pulse width (High)
t_TCKH
15
Input clock pulse width (Low)
t_TCKL
15
Input clock rise time
t
TCKr

Input clock fall time
t
TCKf

ASEBRKAK/BRKACK setup time t
10
ASEBRKS
ASEBRKAK/BRKACK hold time t
10
ASEBRKH
TDI/TMS setup time
t_TDIS
15
TDI/TMS hold time
t
15
TDIH
TDO data delay time
t_TDO
0
ASEBRKAK/BRKACK pulse width t_PINBRK
2
Notes: 1. t indicates the CLKOUT clock cycle.
cyc
2. t indicates the peripheral clock (Pck) cycle.
pcyc
Max. Unit
 ns
 ns
 ns
10 ns
10 ns

t
cyc

t
cyc
 ns
 ns
15 ns

t_Pcyc
Figure
33.64, 33.66
33.64
33.65
33.66
33.67
TCK 1/2V_CCQ
t_TCKcyc
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
V_IL
t_TCKf
V_IH
1/2V_CCQ
t_TCKr
Note: When the clock is input on the TCK pin.
Figure 33.64 TCK Input Timing
Rev. 1.00 Nov. 22, 2007 Page 1642 of 1692
REJ09B0360-0100