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| SH7764 Datasheet, PDF (1603/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
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32.2 Register States in Each Operation Mode
Table 32.2 Register States in Each Operation Mode (1)
Module
Exception
handling
MMU
Cache
On-chip memory
CPG
DMAC
Register
Abbreviation
TRA
EXPEVT
INTEVT
EXPMASK
PTEH
PTEL
TTB
TEA
MMUCR
PTEA
PASCR
IRMCR
CCR
QACR0
QACR1
RAMCR
RAMCR
FRQCR
PLLCR
VDC2CLKCR
SAR0
DAR0
TCR0
CHCR0
SAR1
DAR1
Power-on Reset
Undefined
H'0000 0000
Undefined
H'0000 0000
Undefined
Undefined
Undefined
Undefined
H'0000 0000
H'0000 xxx0
H'0000 0000
H'0000 0000
H'0000 0000
Undefined
Undefined
H'0000 0000
H'0000 0000
H'x032 0044*1
H'0000 E001
H'0000 0080
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Section 32 List of Registers
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 1547 of 1692
REJ09B0360-0100
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