SH7764 Datasheet, PDF (402/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.9.3 Bus Requests from External Devices
This module has the arbitration function in which the bus mastership is given to an external device
when a bus request is issued from the external device.
In the normal state, this LSI has the bus mastership. Upon receiving the bus request from an
external device, this LSI gives permission to use the bus and releases the bus. While the bus is
released, all the signals connected to SRAM or SDRAM are driven to the high-impedance state
except some signals. In the following descriptions, the external devices that issue a bus request are
referred to as slaves.
In this LSI, there are several bus masters: the SuperHyway bus modules such as the CPU and
DMAC, the pixel bus modules, and the LCDC. In addition, when refresh control is carried out for
the connected SDRAM, the SDRAM refresh request can also be a bus master. When two or more
internal bus masters issue a bus request, arbitration is carried out as described in section 11.9.1,
Arbitration of Accesses between Internal Modules, and section 11.9.2, Multi-Step Arbitration.
When any internal bus master and a slave issue a bus request simultaneously, the priority is given
to the refresh requests, requests from the slaves, and requests from the internal bus masters, in this
order.
When the bus mastership is transferred between a master and a slave, all the bus control signals
are negated prior to bus release in order to prevent malfunction of the connected devices. Also,
after the master or slave has received the bus mastership, it negates the bus control signals prior to
driving the bus. Since both the bus master and slave, between which the bus mastership is
transferred, drive the bus control signals to the same value, the conflicts between the output
buffers can be avoided.
The bus mastership is transferred at the boundary of the bus cycles.
When the bus release request signal (BREQ) is asserted, this module processes all the requests
having been already accepted, outputs the bus acknowledge signal (BACK), and then releases the
bus. When BREQ is negated, this module negates BACK and resumes using the bus.
When a refresh request is issued while this LSI has the bus mastership, this LSI carries out
refreshing operation immediately after completing the current bus cycle. However, when multiple
bus cycles are generated because of data bus width being smaller than the access size, for example,
when a longword access is made to the memory of 8-bit bus width, refreshing operation is
suspended until all the multiple bus cycles have been completed. Refreshing operation is also
suspended during 32-byte data transfer to cache file or for write-back.
Rev. 1.00 Nov. 22, 2007 Page 346 of 1692
REJ09B0360-0100