SH7764 Datasheet, PDF (505/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
INT2B2: Indicates detailed interrupt sources for the SCIF.
Module
SCIF1
SCIF0
Bit
31 to 8
7
6
5
4
3
2
1
0
Source Function
Description
—
TXI1
BRI1
These bits are always read as 0. The
write value should always be 0.
SCIF channel 1 transmit FIFO data
empty interrupt
SCIF channel 1 break interrupt or
overrun error interrupt
Indicates SCIF interrupt
sources. This register
indicates the SCIF
interrupt sources even if
mask setting is made in
the interrupt mask
register for them.
RXI1
SCIF channel 1 receive FIFO data full
interrupt or receive data ready
interrupt
ERI1 SCIF channel 1 receive error interrupt
TXI0
SCIF channel 0 transmit FIFO data
empty interrupt
BRI0
SCIF channel 0 break interrupt or
overrun error interrupt
RXI0
SCIF channel 0 receive FIFO data full
interrupt or receive data ready
interrupt
ERI0 SCIF channel 0 receive error interrupt
INT2B3: Indicates detailed interrupt sources for the DMAC.
Module
DMAC
Bit
Source Function
Description
31 to 13 —
12
DMAE
11 to 6 —
These bits are always read as 0. The
write value should always be 0.
DMA channels 0 to 5 address error
interrupt
These bits are always read as 0. The
write value should always be 0.
Indicates DMAC
interrupt sources. This
register indicates DMAC
interrupt sources even if
mask setting is made in
the interrupt mask
register for them.
5
DMINT5
Channel 5 DMA transfer end/half-end
interrupt
4
DMINT4
Channel 4 DMA transfer end/half-end
interrupt
3
DMINT3
Channel 3 DMA transfer end/half-end
interrupt
Rev. 1.00 Nov. 22, 2007 Page 449 of 1692
REJ09B0360-0100