SH7764 Datasheet, PDF (677/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.2 Input/Output Pins
Table 18.1 lists the pin configurations relating to the SSI.
Table 18.1 Pin Configuration
Pin Name
AUDIO_CLK[5:0]
SSISCK[5:0]
SSIWS[5:0]
SSIDATA[5:0]
Function
Audio clock
Serial bit clock
Word select
Serial data
I/O
Input
I/O
I/O
I/O
Description
Divider input clock for SSI_CH0 to SSI_CH5
(oversampling clock)
Serial bit clock for SSI_CH0 to SSI_CH5
Serial word select signal for SSI_CH0 to SSI_CH5
Serial data for SSI_CH0 to SSI_CH5
18.3 Register Descriptions
Table 18.2 shows the SSI_DMAC0 register configuration. Table 18.3 shows the register state in
each operating mode.
Table 18.2 SSI_DMAC0 Register Configuration
Channel Register Name
0
DMA mode register 0
RDMA transfer source
address register 0
RDMA transfer word
count register 0
WDMA transfer
destination address
register 0
WDMA transfer word
count register 0
DMA control register 0
Transmit suspension
block counter 0
Transmit suspension
transfer data register 0
Abbreviation R/W
SSIDMMR0 R/W
SSIRDMADR0 R/W
Area P4
Address
H'FF40 1000
H'FF40 1008
Area 7
Address
Access
Size
H'1F40 1000 32
H'1F40 1018 32
SSIRDMCNTR0 R/W H'FF40 1010 H'1F40 1010 32
SSIWDMADR0 R/W H'FF40 1018 H'1F40 1018 32
SSIWDMCNTR0 R/W H'FF40 1020 H'1F40 1020 32
SSIDMCOR0 R/W H'FF40 1028 H'1F40 1028 32
SSISTPBLCNT0 R/W H'FF40 1030 H'1F40 1030 32
SSISTPDR0 R/W H'FF40 1038 H'1F40 1038 32
Rev. 1.00 Nov. 22, 2007 Page 621 of 1692
REJ09B0360-0100