SH7764 Datasheet, PDF (723/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
13
SCKP
0
R/W Serial Bit Clock Polarity
0: SSIWS[5:0] and SSIDATA[5:0] change at the falling
edge of SSISCK[5:0] (sampled at the rising edge of
SSISCK[5:0]).
1: SSIWS[5:0] and SSIDATA[5:0] change at the rising
edge of SSISCK[5:0] (sampled at the falling edge of
SSISCK[5:0]).
SCKP = 0 SCKP = 1
SSIDATA[5:0] input
sampling timing in receive
mode (TRMD = 0)
SSISCK[5:0] SSISCK[5:0]
rising edge falling edge
SSIDATA[5:0] output
change timing in transmit
mode (TRMD = 1)
SSISCK[5:0] SSISCK[5:0]
falling edge rising edge
SSIWS[5:0] input sampling
timing in slave mode
(SWSD = 0)
SSISCK[5:0] SSISCK[5:0]
rising edge falling edge
SSIWS[5:0] output change
timing in master mode
(SWSD = 1)
SSISCK[5:0] SSISCK[5:0]
falling edge rising edge
12
SWSP
0
R/W Serial Word Selection Signal (WS) Polarity
0: SSIWS[5:0] is low for the first channel, high for the
second channel
1: SSIWS[5:0] is high for the first channel, low for the
second channel
11
SPDP
0
R/W Serial Padding Polarity
0: Padding bits are low
1: Padding bits are high
When MUEN = 1, the padding bits are low. (The MUTE
function has higher priority than padding bits.)
10
SDTA
0
R/W Serial Data Alignment
0: Serial data is transmitted or received first, followed
by padding bits.
1: Padding bits are transmitted or received first,
followed by serial data.
Rev. 1.00 Nov. 22, 2007 Page 667 of 1692
REJ09B0360-0100