SH7764 Datasheet, PDF (1180/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
• REL = 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP CODE = 1011_0110
Reserve (all 0)
Draw Mode
Sign extended Sign
Base Address (longword address)
00
0000
TDX (8 ≤ TDX ≤ 4088)
00 0 0 0 0 0
TDY (1 ≤ TDY ≤ 4095)
0000
TXOFS (0 ≤ TXOFS ≤ TDX − 1)
n (1 ≤ n ≤ 65535)
Reserve (all 0)
0 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63)
Sign DX2 (-128 ≤ DX2 ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) Sign DX1 (-128 ≤ DX1 ≤ 127) Sign DY1 (-128 ≤ DY1 ≤ 127)
Sign
:
Sign
:
Sign
:
Sign
:
Sign
:
Sign
:
Sign
:
Sign
:
Sign DXn (-128 ≤ DXn ≤ 127) Sign DYn (-128 ≤ DYn ≤ 127) Sign DXn-1 (-128 ≤ DXn-1 ≤ 127) Sign DYn-1 (-128 ≤ DYn-1 ≤ 127)
Notes: 1. Adding the address (longword: 32-bit units) where the command code is located to the
Base Address (longword: 32-bit units) must result in a quad word address (64-bit units).
2. When W = 0, set TDY to 1.
3. When n = 0, correct operation is not guaranteed.
4. When n is an odd number, insert a dummy word of 0 at the end.
1. Code
B'10110110
2. Rendering Attributes
Multi-Valued
Source
O
Reference Data
Binary Source Binary Work
Specified
Color
Drawing Destination
Rendering
O
Work
Draw Mode
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
MTRE Fixed CLIP RCLIP STRANS Fixed Fixed SS (0) REL
to 0
to 0 to 0
Notes: 1. Clear the SS bit to 0.
2. Set the STYLE bit to 1.
STYLE Fixed NET
(1)
to 0
EOS
COOF AA
b0
Fixed
to 0
Rev. 1.00 Nov. 22, 2007 Page 1124 of 1692
REJ09B0360-0100