SH7764 Datasheet, PDF (853/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.3.3 Reception
When the CPU sets the receive request bit (RR) in the E-DMAC receive request register (EDRRR)
while the receive function is enabled, the E-DMAC reads the descriptor following the previously
used descriptor from the receive descriptor list (or the descriptor indicated by the receive
descriptor start address register (RDLAR) at the initial start time) then enters the receive standby
state. When the EtherC receives a frame for this LSI (with an address enabled for reception by this
LSI), the EtherC stores the receive data in the receive FIFO. Upon receiving the frame for own
station while the RACT bit is set to 1 (valid), the E-DMAC transfers the frame to the receive
buffer specified by RD2. If the data length of a received frame is longer than the buffer length
specified by RD1, the E-DMAC performs a write-back operation to the descriptor (with RFP set to
10 or 00) when the buffer becomes full, then reads the next descriptor. The E-DMAC then
continues to transfer data to the receive buffer specified by the new RD2. When frame reception is
completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC
performs write-back to the relevant descriptor (with RFP set to 11 or 01), and then ends the
receive processing. The E-DMAC then reads the next descriptor and enters the receive standby
state again.
To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the
receive method control register (RMCR). The initial value is 0.
Rev. 1.00 Nov. 22, 2007 Page 797 of 1692
REJ09B0360-0100