SH7764 Datasheet, PDF (751/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

(a) Reception Using SSI_DMAC0 and SSI_DMAC1
Section 18 Serial Sound Interface (SSI)
Start
Release reset,
specify configuration bits
in SSICR
Setup DMA controller
to transfer data
from SSI module to memory
Enable SSI module,
enable DMA,
enable error interrupts
Wait for interrupt
from DMAC or SSI
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
SSI
Yes
Error interrupt?
No
No
Has DMAC Rx data
been completed?
Yes
Yes
More data
to be received?
No
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
Reset SSI module if required
End*
Note: * When SSI error interrupt occurs (underflow/overflow), back to start
and execute flow again.
Figure 18.21 Reception Using SSI_DMAC0 and SSI_DMAC1
Rev. 1.00 Nov. 22, 2007 Page 695 of 1692
REJ09B0360-0100