SH7764 Datasheet, PDF (1503/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
7, 6
CD
All 0
R/W Bus Select
Specifies the bus to be included in the match conditions.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Operand bus for operand access
Others: Reserved (setting prohibited)
5, 4
ID
All 0
R/W Instruction Fetch/Operand Access Select
Specifies the instruction fetch cycle or operand access
cycle as the match condition.
00: Instruction fetch cycle or operand access cycle
01: Instruction fetch cycle
10: Operand access cycle
11: Instruction fetch cycle or operand access cycle
3
—
0
R Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
2, 1
RW
All 0
R/W Bus Command Select
Specifies the read/write cycle as the match condition.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Read cycle or write cycle
01: Read cycle
10: Write cycle
11: Read cycle or write cycle
0
CE
0
R/W Channel Enable
Validates/invalidates the channel. If this bit is 0, all the
other bits of this register are invalid.
0: Invalidates the channel.
1: Validates the channel.
Rev. 1.00 Nov. 22, 2007 Page 1447 of 1692
REJ09B0360-0100