SH7764 Datasheet, PDF (732/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
0
IDST
1
R
Idle Mode Status Flag
This bit indicates that the serial bus operation has been
stopped.
This bit is cleared if EN = 1 and the serial bus is
currently active.
This bit can be set to 1 automatically under the
following conditions.
• SSI_CH0 to SSI_CH5 = Serial bus master
transmitter (SWSD = 1 and TRMD = 1)
This bit is set to 1 if the EN bit is cleared to 0 and
data written in SSITDR0 to SSITDR5 has been
output from serial data I/O pins (SSIDATA0 to
SSIDATA5).
• SSI_CH0 to SSI_CH5 = Serial bus master receiver
(SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
• SSI_CH0 to SSI_CH5 = Slave transmitter/ receiver
(SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
Note: If the external device stops the serial bus clock
before the current system word is completed,
then this bit will never be set.
Note: * These bits are readable/writable bits. If writing 0, these bits are initialized, although
writing 1 is ignored.
Rev. 1.00 Nov. 22, 2007 Page 676 of 1692
REJ09B0360-0100