SH7764 Datasheet, PDF (497/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Function
Description
16
SSI_ACH1 1
15
SSI_ACH0 1
14
SSI_ADMA0 1
13
G2D
1
12 to 9 —
All 1
8
DMAC
1
7
H-UDI
1
6
—
1
R/W Masks SSI_A (SSICH1) interrupts Masks interrupts for
R/W Masks SSI_A (SSICH0) interrupts ^{each peripheral}
module.
R/W Masks SSI_A (SSIDMA0) interrupts _{[When writing]}
R/W Masks G2D interrupts
0: Invalid
R/W Reserved
1: Interrupts are
These bits are always read as 1. _masked
The write value should always be 1. _{[When reading]}
R/W Masks DMAC interrupts
0: No mask setting
R/W Masks H-UDI interrupts
1: Mask setting
R Reserved
This bit is always read as 1. The
write value should always be 1.
5
WDT
1
R/W Masks WDT interrupts
4
SCIF1
1
R/W Masks SCIF1 interrupts
3
SCIF0
1
R/W Masks SCIF0 interrupts
2
—
1
R Reserved
This bit is always read as 1. The
write value should always be 1.
1
TMU1
1
R/W Masks TMU1 interrupts
0
TMU0
1
R/W Masks TMU0 interrupts
Rev. 1.00 Nov. 22, 2007 Page 441 of 1692
REJ09B0360-0100