SH7764 Datasheet, PDF (348/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W Description
26 to 24 IWRWD2 to 111
IWRWD0
R/W Idle Cycles between Read and Write Access Cycles to
Different Areas
These bits specify the number of idle cycles to be
inserted after a read access to the memory connected
to area 0.
The idle cycles specified in these bits are inserted
between a read access cycle to area 0 and a write
access cycle to area 3.
000: No idle cycles inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
23

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
22 to 20 IWRWS2 to 111
IWRWS0
R/W Idle Cycles between Read and Write Access Cycles to
Same Area (Area 0)
These bits specify the number of idle cycles to be
inserted after a read access to the memory connected
to area 0.
The idle cycles specified in these bits are inserted
between consecutive read and write access cycles to
the same area (area 0).
000: No idle cycles inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Rev. 1.00 Nov. 22, 2007 Page 292 of 1692
REJ09B0360-0100