SH7764 Datasheet, PDF (765/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.2 EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register that indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the PFROI, LCHNG, MPD, and ICD
bits, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that
generate interrupts, the interrupt can be enabled or disabled by the corresponding bit in ECSIPR.
The interrupts generated due to this status register are indicated in ECI bit in EESR of the E-
DMAC.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
— BFR PFROI — LCHNG MPD ICD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 6 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
BFR
0
R/W Continuous Broadcast Frame Reception Interrupt
(Interrupt Source)
Indicates that Broadcast frames have been received
continuously.
4
PFROI 0
R/W PAUSE Frame Retransmit Retry Over
Indicates whether the retransmit count for
retransmitting a PAUSE frame when flow control is
enabled has exceeded the retransmit upper-limit set in
the automatic PAUSE frame retransmit count register
(TPAUSER).
0: PAUSE frame retransmit count has not exceeded the
upper limit
1: PAUSE frame retransmit count has exceeded the
upper limit
Rev. 1.00 Nov. 22, 2007 Page 709 of 1692
REJ09B0360-0100