SH7764 Datasheet, PDF (454/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
CH0 transfer source
CPU
DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1
CPU
DMA CH1
Burst mode
DMA CH0 and CH1
Burst mode
DMA CH1
Burst mode
CH1 transfer source
Priority: CH0 > CH1
CH0: Cycle steal mode
CH1: Burst mode
Figure 12.10 Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes according to the specification shown in figure 12.3.
However, the channel in cycle steal mode cannot be mixed with the channel in burst mode.
12.4.4 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit
of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are
also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.
Figure 12.11 shows a flowchart of this procedure.
Rev. 1.00 Nov. 22, 2007 Page 398 of 1692
REJ09B0360-0100