SH7764 Datasheet, PDF (225/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value R/W Description
3
R1
0
R/W Re-Fetch Inhibit 1 after Register Change
When a register allocated in addresses H'FF200000 to
H'FF2FFFFF is changed, this bit controls whether re-
fetch is performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
2
LT
0
R/W Re-Fetch Inhibit after LDTLB Execution
This bit controls whether re-fetch is performed for the
next instruction after the LDTLB instruction has been
executed.
0: Re-fetch is performed
1: Re-fetch is not performed
1
MT
0
R/W Re-Fetch Inhibit after Writing Memory-Mapped TLB
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped
ITLB/UTLB while the AT bit in MMUCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
0
MC
0
R/W Re-Fetch Inhibit after Writing Memory-Mapped IC
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped IC while
the ICE bit in CCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
Rev. 1.00 Nov. 22, 2007 Page 169 of 1692
REJ09B0360-0100