SH7764 Datasheet, PDF (1346/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.3.3 Command Code Register (FLCMCDR)
FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in
command access or sector access.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CMD[15:8]
CMD[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 16 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 8 CMD[15:8] H'00
R/W Specify a command code to be issued in the second
command stage.
7 to 0 CMD[7:0] H'00
R/W Specify a command code to be issued in the first
command stage.
Rev. 1.00 Nov. 22, 2007 Page 1290 of 1692
REJ09B0360-0100