SH7764 Datasheet, PDF (273/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches
Initial
Bit
Bit Name Value
8
RP
0
7
IC2W
0
6
OC2W
0
5
ICWPD
0
4 to 0 
All 0
R/W Description
R/W On-Chip Memory Protection Enable Bit
For details, see section 9.4, On-Chip Memory
Protective Functions.
R/W IC Two-Way Mode bit
0: IC is a four-way operation
1: IC is a two-way operation
For details, see section 8.4.3, IC Two-Way Mode.
R/W OC Two-Way Mode bit
0: OC is a four-way operation
1: OC is a two-way operation
For details, see section 8.3.6, OC Two-Way Mode.
R/W IC Way Prediction Stop
Selects whether the IC way prediction is used.
0: Instruction cache performs way prediction.
1: Instruction cache does not perform way prediction.
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Rev. 1.00 Nov. 22, 2007 Page 217 of 1692
REJ09B0360-0100