SH7764 Datasheet, PDF (753/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
When an underflow or overflow error condition is met, the CHNO[1:0] and SWNO bits in SSISR0
to SSISR5 can be used to recover SSI_CH0 to SSI_CH5 to a known status. When an underflow or
overflow occurs, the host CPU can read the number of channels and the number of system words
to determine what point the serial audio stream has reached. In the transmitter case, the host CPU
can skip forward through the data it wants to transmit until it finds the sample data that matches
what SSI_CH0 to SSI_CH5 are expecting to transmit next, and so resynchronize with the audio
data stream. In the receiver case, the host CPU can skip forward storing null sample data until it is
ready to store the sample data that SSI_CH0 to SSI_CH5 are indicating that it will receive next to
ensure consistency of the number of received data, and so resynchronize with the audio data
stream.
(6) Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD in SSICR = 0), SSI_CH0 to SSI_CH5 are in
clock slave mode, then the bit clock that is used in the shift register is derived from the
SSISCK[5:0] pins.
If the serial clock direction is set to output (SCKD in SSICR = 1), SSI_CH0 to SSI_CH5 are in
clock master mode, and the shift register uses the bit clock derived from the AUDIO_SCK[5:0]
input pins or its clock divided. This input clock is then divided by the ratio in the serial
oversampling clock division ratio (CKDV) bit in SSICR0 to SSICR5 and used as the bit clock in
the shift register.
In either case, the SSISCK[5:0] pin outputs are the same as the bit clock.
Rev. 1.00 Nov. 22, 2007 Page 697 of 1692
REJ09B0360-0100