SH7764 Datasheet, PDF (1476/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Power-Down Mode
28.4 Sleep Mode
28.4.1 Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of the CPU registers remain unchanged. On-chip peripheral
modules continue to operate, and the clock output on the CLKOUT pin also continues. In sleep
mode, a high level is output to the STATUS1 pin and a low level to the STATUS0 pin.
28.4.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ1, IRQ0 or on-chip peripheral module interrupt)
or a reset.
Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and
SSR to the stack before executing the SLEEP instruction.
(1) Canceling with Interrupt
When an NMI, IRQ1, IRQ0 or on-chip peripheral module interrupt occurs, sleep mode is canceled
and interrupt exception handling is executed. A code indicating the interrupt source is set in
INTEVT.
(2) Canceling with Reset
Sleep mode is canceled by a power-on reset caused by the PRESET pin or watchdog timer
overflow.
Rev. 1.00 Nov. 22, 2007 Page 1420 of 1692
REJ09B0360-0100