SH7764 Datasheet, PDF (31/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

33.4.4 INTC Module Signal Timing.............................................................................. 1603
33.4.5 DMAC Module Signal Timing ........................................................................... 1605
33.4.6 TMU Module Signal Timing .............................................................................. 1605
33.4.7 IIC Module Signal Timing.................................................................................. 1606
33.4.8 SCIF Module SignalTiming................................................................................ 1608
33.4.9 SSI Module Signal Timing ................................................................................. 1609
33.4.10 ATAPI Interface Module Signal timing.............................................................. 1612
33.4.11 USB Module Signal Timing ............................................................................... 1640
33.4.12 GPIO Signal Timing ........................................................................................... 1641
33.4.13 H-UDI Module Signal Timing............................................................................ 1642
33.4.14 EtherC Module Signal Timing............................................................................ 1644
33.4.15 FLCTL Module Signal Timing ........................................................................... 1648
33.4.16 LCDC Module Signal Timing ............................................................................ 1652
33.4.17 VDC2 Module Signal Timing............................................................................. 1654
33.5 AC Characteristics Measurement Conditions .................................................................. 1657
Appendix .......................................................................................................1659
A. CPU Operation Mode Register (CPUOPM) .................................................................... 1659
B. Instruction Prefetching and Its Side Effects..................................................................... 1661
C. Speculative Execution for Subroutine Return.................................................................. 1662
D. Version Registers (PVR, PRR) ........................................................................................ 1663
E. Pin State ........................................................................................................................... 1665
F. Pin Treatment When Not in Use ...................................................................................... 1675
G. Type Name....................................................................................................................... 1683
H. Package Dimensions ........................................................................................................ 1684
Index
.......................................................................................................1685
Rev. 1.00 Nov. 22, 2007 Page xxxi of lvi