SH7764 Datasheet, PDF (168/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
(3) Initial Page Write Exception
• Source: TLB is hit in a store access, but dirty bit D = 0
• Transition address: VBR + H'00000100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Initial_write_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 0080;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}
Rev. 1.00 Nov. 22, 2007 Page 112 of 1692
REJ09B0360-0100