SH7764 Datasheet, PDF (611/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
Section 16 I²C Bus Interface (IIC)
16.1 Features
The I²C bus interface has the following features:
• Supports the Philips I²C bus interface
• Multi-master compatible
• Seven- or ten-bit address compatible master
• Seven-bit slave address
• Fast mode compatible
• Variable clock frequencies
Figure 16.1 shows a block diagram for the I²C bus interface.
SCL
Clock Generator
SCL
SDA
Clock Filter
Data Filter
Master
Slave
SDA
Control/Status
Register
Tx DATA
Rx DATA
Figure 16.1 Block Diagram for I²C Bus Interface
Rev. 1.00 Nov. 22, 2007 Page 555 of 1692
REJ09B0360-0100