SH7764 Datasheet, PDF (441/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCRn (n=0, 1) as shown in table 12.6. The source of the transfer request does not have to be
the data transfer source or destination.
Table 12.6 Selecting External Request Detection with DL, DS Bits
CHCRn (n=0, 1)
DL
DS
0
0
1
1
0
1
Detection of External Request
Low level detection (initial value; DREQ)
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 12.7 Selecting External Request Detection with DO Bit
CHCR
DO
0
1
External Request
Overrun 0 (initial value)
Overrun 1
Rev. 1.00 Nov. 22, 2007 Page 385 of 1692
REJ09B0360-0100