SH7764 Datasheet, PDF (667/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.4 Functional Description
This module supports a primary channel as a host. The master/slave configuration is also
supported as defined in the ATAPI interface specification. The ATAPI interface's read/write FIFO
buffers are designed to implement data transfer of up to 66 Mbyte/s in Ultra DMA and 16 Mbyte/s
in multiword DMA modes. This module supports the 3.3-V I/O interface.
17.4.1 Data Transfer Modes
ATAPI interface control register supports the PIO transfer, multiword DMA transfer, and Ultra
DMA transfer mode. It initiates transfer modes and sets a specific ATAPI interface timing which
is different in each mode.
PIO modes 0 to 4, multiword DMA modes 0 to 2 and Ultra DMA mode 0 to 4 (up to 66 Mbyte/s)
are supported.
For both multiword DMA and Ultra DMA data transfers, the pixel bus can be used while the I/O
bus can only be used for the PIO transfer.
Table 17.5 Data Transfer Modes
Data Transfer Mode
Internal Operation and
Internal Register
DMA Data Transfer between ATA Device
and Pixel Bus
PIO Data Transfer Multiword DMA
Ultra DMA
FIFO operation
Bypass*
Used
Used
BUSSEL bit in control
register
Don't care
1
1
UDMAEN bit in control
register
Don't care
0
1
START/STOP bit in control
register
Not used
Used
Used
Note: * The CPU accesses the ATA device in PIO mode. For DMA transfer in this table, data is
transferred between the ATAPI device and the memory.
17.4.2 Descriptor Function
A DMA transfer for which continuous memory areas are specified can be used in this module. Set
individual DMA start addresses and DMA transfer counts in the descriptor table.
Rev. 1.00 Nov. 22, 2007 Page 611 of 1692
REJ09B0360-0100