SH7764 Datasheet, PDF (1316/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Initial
Bit
Bit Name Value
R/W
9
EX_V_
0
R/W
TYPE
8
EX_H_
0
R/W
TYPE
7, 6

All 0
R
5
VSYNC_ 0
R/W
TYPE
4
HSYNC_ 0
R/W
TYPE
3
DEV_TYPE 0
R/W
2
DEH_TYPE 0
R/W
1
DEC_TYPE 0
R/W
0
COM_TYPE 0
R/W
Description
Controls whether to invert the external VSYNC
input.
0: Does not invert the external VSYNC input
1: Inverts the external VSYNC input
Controls whether to invert the external HSYNC
input.
0: Does not invert the external HSYNC input
1: Inverts the external HSYNC input
Reserved
These bits are always read as 0. The write value
should always be 0.
Controls whether to invert the VSYNC/SPS output.
0: Does not invert the VSYNC/SPS output.
1: Inverts the VSYNC/SPS output.
Controls whether to invert the HSYNC/SPL output.
0: Does not invert the HSYNC/SPL output
1: Inverts the HSYNC/SPL output
Controls whether to invert the DEV/CLS output.
0: Does not invert the DEV/CLS output
1: Inverts the DEV/CLS output
Controls whether to invert the DEH/LP output.
0: Does not invert the DEH/LP output
1: Inverts the DEH/LP output
Controls whether to invert the DEC/PS output.
0: Does not invert the DEC/PS output
1: Inverts the DEC/PS output
Controls whether to invert the COM/CDE output.
0: Does not invert the COM/CDE output
1: Inverts the COM/CDE output
Rev. 1.00 Nov. 22, 2007 Page 1260 of 1692
REJ09B0360-0100