SH7764 Datasheet, PDF (403/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Refreshing operation is also suspended in the bus-released state because refreshing operation is
impossible in that state. When a refresh request is issued in the bus-released state, this LSI negates
BACK to request the external device currently having the bus mastership to release the bus. The
external device should negate BREQ when BACK is negated. This returns the bus mastership to
this LSI allowing this LSI to carry out necessary processing.
Since the bus mastership cannot be returned immediately after BACK negation, refreshing
operation may be suspended for a longer time than the time required when this LSI has the bus
mastership. Due to this, the specified refresh interval may not be kept. Therefore, in the bus-
released state, a refresh request is issued at the half interval of the interval that is set by the DRAM
refresh interval bits (DRI[11:0] in MIM).
11.9.4 Bus Release and Recovery Sequences
This LSI has the bus mastership unless it receives a bus request from another device.
In response to assertion (low level) of the bus request (BREQ) from an external device, this LSI
asserts (low level) the bus acknowledge (BACK) to release the bus immediately after completing
all the accepted requests from internal bus masters. If there is no bus request for refreshing, this
LSI negates (high level) BACK and resumes using the bus upon negation (high level) of BREQ,
which indicates that the slave has released the bus.
If there is any bus request for refreshing in the bus-released state, this LSI first negates the bus
acknowledge (BACK) and then resumes using the bus upon negation of BREQ, which indicates
that the slave has released the bus.
When releasing the bus, this LSI drives all the bus control signals related to bus interfacing to the
high-impedance state except the SDRAM interface signal CKE, the bus arbitration signal BACK,
and the DMA transfer control signals DACK0, DACK1, DTEND0, and DTEND1.
In addition, this LSI issues the precharge command to the active banks of the SDRAM and
releases the bus after the command has been completed.
The specific bus release sequence is described below. First, BACK is asserted in synchronization
with the rising edge of the clock pulse, and in synchronization with the rising edge of the next
clock pulse to the BACK assertion, the address bus and data bus are driven to the high-impedance
state. Simultaneously, the bus control signals (BS, CSn, RAS, CAS, WEn, RD, R/W, and DQMn)
are driven to the high-impedance state. These bus control signals are negated at least one clock
cycle before driven to the high-impedance state. BREQ is sampled at the rising edge of the clock
pulses.
Rev. 1.00 Nov. 22, 2007 Page 347 of 1692
REJ09B0360-0100