SH7764 Datasheet, PDF (849/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
26 to 0 RFS
All 0
R/W Receive Frame Status
RF26 to RF10 [Reserved (The write value should
always be 0.)];
RFS9 [Receive FIFO Overflow (corresponding to the
RFOF bit in EESR)]:
When set to 1, this bit indicates that a receive
FIFO overflow has occurred terminating the frame
halfway and that the frame has been written back.
(causing RFE to be set)
TFS8 [Detect Receive Abort];
When set to 1, this bit indicates that the abort
signal is set to 1 during frame transmission.
(causing RFE to be set)
RFS7 [Multicast address frame received
(corresponding to the RMAF bit in EESR)];
RFS6 and RFS5 [Reserved (The write value should
always be 0.)];
RFS4 [Residual-bit frame receive error
(corresponding to the RRF bit in EESR)];
RFS3 [Long frame receive error (corresponding to the
RTLF bit in EESR)];
RFS2 [Short frame receive error (corresponding to
the RTSF bit in EESR)];
RFS1 [PHY-LSI receive error (corresponding to the
PRE bit in EESR)];
RFS0 [CRC error detected in receive frame
(corresponding to the CERF bit in EESR)]:
When set to 1, these bits indicate that RFS8 to
RFS1 have been set to 1 during frame reception.
(Although RFE is normally set when these bits are
set to 1, it can be prevented from being set by so
settingTRSCER.)
Rev. 1.00 Nov. 22, 2007 Page 793 of 1692
REJ09B0360-0100