SH7764 Datasheet, PDF (339/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.4.10 Linear-to-Tiled Memory Address Translation Area Start Address Mask Register
(LTAMn)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LTAM[8:0]

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W
63 to 29 
All 0 R
28 to 20 LTAM8 to H'000 R/W
LTAM0
19 to 0 
All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Linear-to-Tiled Memory Address Translation Start
Address Mask
These bits specify the range for comparison between
the LTAD bits and a real address.
Reserved
These bits are always read as 0. The write value
should always be 0.
In the LTAM8 to LTAM0 bits, specify a physical address in the unified memory. The data should
contain contiguous 1s from the left. So, one of (H'000), (H'100), H'180, H'1C0, H'1E0, H'1F0,
H'1F8, H'1FC, H'1FE, and H'1FF should be specified.
Note: The unified memory space of this LSI consists of areas 1 and 2, which are 64 Mbytes
each. Accordingly, (H'000) and (H'100) should not be specified.
Rev. 1.00 Nov. 22, 2007 Page 283 of 1692
REJ09B0360-0100