SH7764 Datasheet, PDF (36/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 12.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
(DREQ Low Level Detection) ...................................................................................393
Figure 12.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
(DREQ Low Level Detection) ...................................................................................394
Figure 12.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
(DREQ Low Level Detection) ...................................................................................394
Figure 12.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .......395
Figure 12.10 Bus State when Multiple Channels are Operating....................................................398
Figure 12.11 DMA Transfer Flowchart.........................................................................................399
Figure 12.12 Reload Mode Transfer..............................................................................................401
Figure 12.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection...............402
Figure 12.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection..............402
Figure 12.15 Example of DREQ Input Detection in Burst Mode Edge Detection ........................403
Figure 12.16 Example of DREQ Input Detection in Burst Mode Level Detection .......................403
Figure 12.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) .............................404
Figure 12.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)..................................405
Section 13 Interrupt Controller (INTC)
Figure 13.1 Block Diagram of INTC.............................................................................................410
Figure 13.2 On-Chip Module Interrupt Priority ............................................................................457
Figure 13.3 Interrupt Operation Flowchart....................................................................................463
Figure 13.4 Example of Interrupt Handling Routine .....................................................................466
Figure 13.5 The time requested to detect interrupts from IRQ1 and IRQ0 ...................................466
Section 14 Timer Unit (TMU)
Figure 14.1 Block Diagram of TMU .............................................................................................470
Figure 14.2 Example of Count Operation Setting Procedure ........................................................482
Figure 14.3 TCNT Auto-Reload Operation ...................................................................................483
Figure 14.4 Count Timing when Operating on Internal Clock ......................................................483
Figure 14.5 Count Timing when Operating on External Clock .....................................................484
Figure 14.6 Operation Timing when Using Input Capture Function .............................................485
Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.1 Block Diagram of SCIF..............................................................................................491
Figure 15.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits) ...............................................................530
Figure 15.3 Sample Flowchart for SCIF Initialization ..................................................................533
Figure 15.4 Sample Flowchart for Transmitting Serial Data.........................................................534
Figure 15.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit) ...............................536
Figure 15.6 Example of Operation Using Modem Control (CTS).................................................536
Figure 15.7 Sample Flowchart for Receiving Serial Data .............................................................537
Rev. 1.00 Nov. 22, 2007 Page xxxvi of lvi