SH7764 Datasheet, PDF (537/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Timer Unit (TMU)
14.4 Operation
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR).
Each TCNT performs count-down operation. The channels have an auto-reload function that
allows cyclic count operations, and can also perform external event counting. Channel 2 also has
an input capture function.
14.4.1 Counter Operation
When one of bits STR0 to STR2 in TSTR1 and TSTR0 is set to 1, the TCNT for the
corresponding channel starts counting. When TCNT underflows, the UNF flag in TCR is set. If
the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same
time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload
function).
(1) Example of Count Operation Setting Procedure
Figure 14.2 shows an example of the count operation setting procedure.
Rev. 1.00 Nov. 22, 2007 Page 481 of 1692
REJ09B0360-0100