SH7764 Datasheet, PDF (1708/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
33.4.16 LCDC Module Signal Timing
Table 33.34 LCDC Module Signal timing
Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35,
Ta = –20 to 85°C, –40 to 85°C
Item
Symbol
LCD_CLK input clock frequency t
FREQ
LCD_CLK input clock rise time
t_r
LCD_CLK input clock fall time
t_f
LCD_CLK input clock duty
t
DUTY
Clock (LCD_CL2) cycle time
t
CC
Clock (LCD_CL2) high pulse width t
CHW
Clock (LCD_CL2) low pulse width t
CLW
Clock (LCD_CL2) transition time t_CT
(rise/fall)
Data (LCD_DATA) delay time
t_DDdo
Display permission (LCK_CL1)
t_IDdo
delay time
Horizontal synchronized signal t
HDdo
(LCD_CL1) delay time
Vertical synchronized signal
t
VDdo
(LCD_FLM) delay time
Min.



90
25
7
7

–3.5
–3.5
–3.5
–3.5
Max.
54
3
3
110



3
3
3
3
3
Unit
MHz
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
Figure
33.81
Rev. 1.00 Nov. 22, 2007 Page 1652 of 1692
REJ09B0360-0100